In T4, all bus signals are deactivated in preparation for the next bus cycle. If the bus cycle happens to be a read bus cycle, the data bus is sampled at the end of T3. (More detail is provided in Section 9–5.) This clocking period is provided to allow the memory time to access data. If READY is low at this time, T3 becomes a wait state (Tw). READY is sampled at the end of T2, as illustrated in Figure 9–11. If this hap- pens to be a write bus cycle, the data are sent out to the memory or I/O through the data bus. The DEN signal turns on the data bus buffers, if they are present in the system, so the memory or I/O can receive data to be written, or so the microprocessor can accept the data read from the memory or I/O for a read operation. These events cause the memory or I/O device to begin to perform a read or a write. The IO>M or M>IO signal indicates whether the address bus contains a memory address or an I/O device (port) number.ĭuring T2, the 8086/8088 microprocessors issue the RD or WR signal, DEN, and in the case of a write, the data to be written appear on the data bus. (The address/data bus is multiplexed and sometimes contains memory-addressing inf ormation, sometimes data.) Durin g TI, con trol signals ALE, DT>R, and IO>M (8088) or M>IO (8086) are also output. The address of the memory or I/O location is sent out via the address bus and the address/data bus connections. (Because of the internal queue, the 8086/8088 can exe- cute 2.5 million instructions per second in bursts.) Other available versions of these microprocessors operate at much higher transfer rates due to higher clock frequencies.ĭuring the first clocking period in a bus cycle, which is called T1, many things happen. This means that the microprocessor reads or writes data between itself and memory or I/O at a maxi- mum rate of 1.25 million times a second. If the clock is operated at 5 MHz (the basic operating frequency for these two microprocessors), one 8086/8088 bus cycle is complete in 800 ns. Newer microprocessors divide the bus cycle into as few as two clocking periods. Each bus cycle equals four system-clocking periods (T states). The 8086/8088 microprocessors use the memory and I/O in periods called bus cycles. If data are read from the memory (see the simplified timing for read in Figure 9–10), the microprocessor outputs the memory address on the address bus, issues a read memory signal (RD), and accepts the data via the data bus.
If data are written to the memory (see the simplified timing for write in Figure 9–9), the microprocessor outputs the memory address on the address bus, out- puts the data to be written into memory on the data bus, and issues a write (WR) to memory and IO>M = 0 for the 8088 and M>IO = 1 for the 8086. Basic Bus Operation The three buses of the 80-address, data, and control-function exactly the same way as those of any other microprocessor. It is important to note that we discuss only the times that affect memory and I/O interfacing in this section. This section provides insight into the operation of the bus signals and the basic read and write timing of the 8086/8088. A 400 MHz data rate multiplied by 8 Bytes per transfer provides 3,200 MB/s bandwidth, hence the name PC3200.It is essential to understand system bus timing before choosing a memory or I/O device for inter- facing to the 8086 or 8088 microprocessors. The naming convention for finished modules has become its bandwidth, with each module providing 64 data connections for 8 Bytes of data per transfer. (This explains the popularity of "PC100" modules that use 7 ns chips.)ĭouble Data Rate (DDR) technology allows data to be transmitted twice per clock cycle, so DDR SDRAM with a 200 MHz clock rate actually has a 400 MHz data rate, and is referred to as DDR400. This allows a wide range of compatibility for higher speed modules in older systems it is common practice for manufacturers to re-label faster RAM at slower speeds whenever the slower RAM ceases production. For example, 133 MHz SDRAM could operate at 133 MHz, 100 MHz, 66 MHz, or even at speeds of less than 1 MHz, depending on how quickly the system accesses it. By design, DRAM maintains its data only as long as a charge is applied to the cells, so there is no maximum cycle time.
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